Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 166)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 166
6.3.12.13 FPGA Payload Watchdog Clear Register
Any write done by the payload software to this register will be treated as feed and restarts the
FPGA payload watchdog.
6.3.12.14 FPGA-IPMC-Watchdog Threshold Register
The FPGA has an internal watchdog which monitors how the IPMC is normally running. If the
IPMC fails to feed the FPGA according to the time set by this register, the latter will issue a cold
reset to the former. Payload will not be affected by the reset of the IPMC.
The IPMC software writes this register to set the timeout threshold of the FPGA-IPMC
Watchdog. Unit is one second, maximum time is 255s. When "0" is written to it, the watchdog
will be disabled and will never bite. Writing and other data will enable and restart the FPGA-
IPMC-Watchdog.
Table 6-64 FPGA-Payload-Watchdog Threshold Low-byte Register
Address Offset: 0x1B
Bit Description Default Access
7:0 High byte of timeout threshold for FPGA-
Payload-Watchdog, unit is one msec 0xFF LPC: r/w
Table 6-65 FPGA-Payload-Watchdog Clear Register
Address Offset: 0x1C
Bit Description Default Access
7:0 Writing any data will clear the FPGA-Payload-
Watchdog - LPC: w
Table 6-66 FPGA-IPMC-Watchdog Threshold Register
Address Offset: 0x1F
Bit Description Default Access
7:0 Timeout threshold the 'FPGA-IPMC-
Watchdog', unit is one second. 00 IPMC: r/w