Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 144)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 144
3 Framing Error (FE) indicator
When FE is set, it indicates that the received
character did not have a valid (set) stop bit.
FE is cleared every time the CPU reads the
contents of the LSR. In the FIFO mode, this
error is associated with the particular
character in the FIFO to which it applies. This
error is revealed to the CPU when its
associated character is at the top of the FIFO.
The Asynchronous Communications
Element (ACE) tries to resynchronize after a
framing error. To accomplish this, it is
assumed that the framing error is due to the
next start bit. The ACE samples this start bit
twice and then accepts the input data:
1: Framing error occurred
0: No framing error 0 LPC: r
4 Break Interrupt (BI) indicator
When BI is set, it indicates that the received
data input was held low for longer than a full-
word transmission time. A full-word
transmission time is defined as the total time
to transmit the start, data, parity, and stop
bits. BI is cleared every time the CPU reads
the contents of the LSR. In the FIFO mode,
this error is associated with the particular
character in the FIFO to which it applies. This
error is revealed to the CPU when its
associated character is at the top of the FIFO.
When a break occurs, only one 0 character is
loaded into the FIFO. The next character
transfer is enabled after RXD goes to the
marking state for at least two Receiver CLK
samples and then receives the next valid
start bit:
1: Full WORD transmission time exceeded
0: Normal operation 0 LPC: r
Table 6-37 Line Status Register (LSR) (continued)
LPC IO Address: Base + 5
Bit Description Default Access