Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 133)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 133
6.2.5 UART Registers DLAB=0
6.2.5.1 Receiver Buffer Register (RBR)
In non-FIFO mode, the Receiver Buffer Register (RBR) holds the character received by the
UART’s receive shift register. If less than 8-bits are received, the bits are right-justified and the
leading bits are zeroed. Reading the register empties the register and resets the Data Ready
(DR) bit in the line status register to zero. Other bits, errors or otherwise, are not cleared. In
(First In/ First Out) FIFO mode, this register latches the value of the data byte at the top of the
FIFO.
Base + 6 X Modem Status Register (MSR). Read Only
Base + 7 X Scratch Pad Register (SCR).
Base 1 Divisor Latch LSB (DLL)
Base + 1 1 Divisor Latch MSB (DLM)
Table 6-27 UART Register Overview (continued)
LPC IO Address DLAB Bit value Description
Table 6-28 Receiver Buffer Register (RBR) if DLAB=0
LPC IO Address: Base
Bit Description Default Access
7:0 Receiver Buffer register (RBR) Undef. LPC: r