Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 141)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 141
6.2.5.8 Line Status Register (LSR)
This register provides status information to the processor concerning the data transfers. Bits 5
and 6 show information about the transmitter. The rest of the bits contain information about
the receiver.
2 User output control signal (OUT1#):
1: OUT1# output in high state
0: OUT1# output in low state
Not supported 0 LPC: r/w
3 User output control signal (OUT2#):
1: OUT2# output in high state
0: OUT2# output in low state
Not supported 0 LPC: r/w
4 Local loop back diagnostic control
When loop back is activated: Transmitter
TXD is set high. Receiver RXD is
disconnected. Output of Transmitter Shift
Register (TSR) is looped back into the
receiver shift register input. Modem control
inputs are disconnected and modem control
outputs are internally connected to modem
control inputs. Modem control outputs are
forced to the inactive (high) levels:
1: Loop back mode activated
0: Normal operation 0 LPC: r/w
5 Autoflow control enable (AFE):
1: Autoflow control enabled (auto-RTS# and
auto-CTS# or auto-CTS# only enabled)
0: Autoflow control disabled 0 LPC: r/w
7:6 Reserved 0 LPC: r
Table 6-36 Modem Control Register (MCR) (continued)
LPC IO Address: Base + 4
Bit Description Default Access