Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 162)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 162
The operating system should never write to this register.
6.3.12.8 Payload Reset Source for OS Register
The OS reset source register stores the source of the most recent reset as it is done in the BIOS
reset source register. A "one" in the register bit indicates that the associated reset has occurred.
If more than one reset occurs from different sources without clearing the corresponding
register bits, one cannot determine the most recent reset source since more than one bit will
be set. The same situation will happen, if two reset sources go active at the same time.
Table 6-58 Payload Reset Source for BIOS Register
Address Offset: 0x15
Bit Description Default Access
0 Payload Power-on reset
1: Reset occurred RST_N:1 LPC: r/w1c
1 Reserved 0 LPC: r/w1c
2 Front board push button reset payload
request
1: Reset occurred 0 LPC: r/w1c
3 IPMC reset payload request
1: Reset occurred 0 LPC: r/w1c
4 RTM push button reset request
1: Reset occurred 0 LPC: r/w1c
5 FPGA Watchdog reset payload request
1: Reset occurred 0 LPC: r/w1c
6 BIOS reset payload request
1: Reset occurred 0 LPC: r/w1c
7 OS reset payload request
1: Reset occurred 0 LPC: r/w1c