Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 164)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 164
6.3.12.9 IPMC Watchdog Timeout Register
The IPMC SW sets the corresponding bit to signal an IPMC watchdog timeout event. When the
IPMC watchdog timeout bit is set from low to high, the corresponding bits in
Table 6-61 "IPMC
Watchdog Timeout for BIOS Register" and Table 6-62 "IPMC Watchdog Timeout for OS
Register" are set.
6.3.12.10 IPMC Watchdog Timeout for BIOS Register
When the corresponding bits in IPMC Watchdog Timeout Register changes from 0 to 1, this
register will have its bits set to 1. The BIOS software can clear certain bits by writing 1 to it.
This register is only used for communication between the IPMC and the BIOS software. FPGA
will not use these bits by itself. OS should never write to this register.
Table 6-60 IPMC Watchdog Timeout Register
Address Offset: 0x17
Bit Description Default Access
0 IPMC Watchdog Timeout
0: No IPMC Watchdog Timeout
1: IPMC Watchdog Timeout occurred 0 IPMC: r/w
1 IPMC Watchdog Pre-Timeout
0: No IPMC Watchdog Pre-Timeout
1: IPMC Watchdog Pre-Timeout occurred 0 IPMC: r/w
7:2 Reserved 000000 IPMC: r
Table 6-61 IPMC Watchdog Timeout for BIOS Register
Address Offset: 0x18
Bit Description Default Access
0 IPMC Watchdog Timeout
1: IPMC Watchdog Timeout occurred 0 LPC: r/w1c
1 IPMC Watchdog Pre-Timeout
1: IPMC Watchdog Pre-Timeout occurred 0 LPC: r/w1c
7:2 Reserved 000000 LPC: r