Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 146)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 146
6.2.5.9 Modem Status Register (MSR)
The MCR is an 8-bit register that provides the current state of the control lines from the modem
or data set (or a peripheral device emulating a modem) to the processor. In addition to this
current state information, four bits of the Modem Status register provide change information.
Bits 03:00 are set to a logic 1 when a control input from the Modem changes state. They are
reset to logic 0 when the processor reads the Modem Status register.
When bits 0, 1, 2, or 3 are set to logic 1, a Modem Status interrupt is generated if bit 3 of the
Interrupt Enable Register is set.
Table 6-38 Modem Status Register (MSR)
LPC IO Address: Base + 6
Bit Description Default Access
0 Change in Delta Clear-To-Send (DCTS)
indicator
DCTS indicates that the CTS# input has
changed state since the last time it was read
by the CPU. When DCTS is set (autoflow
control is not enabled and the modem status
interrupt is enabled), a modem status
interrupt is generated. When autoflow
control is enabled (DCTS is cleared), no
interrupt is generated:
1: Change in state of CTS# input since last
read
0: No change in state of CTS# input since last
read 0 LPC: r/w
1 Change in Delta Data Set Ready (DDSR)
indicator
DDSR indicates that the DSR# input has
changed state since the last time it was read
by the CPU. When DDSR is set and the
modem status interrupt is enabled, a modem
status interrupt is generated:
1: Change in state of DSR# input since last
read
0: No change in state of DSR# input since last
read 0 LPC: r/w