Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 138)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 138
6.2.5.6 Line Control Register (LCR)
The system programmer of the LCR specifies the format of the asynchronous data
communications exchange. The serial data format consists of a start bit (logic 0), five to eight
data bits, an optional parity bit, and one or two stop bits (logic 1). The LCR has bits for accessing
the divisor latch and causing a break condition. The programmer can also read the contents of
the Line Control Register. The read capability simplifies system programming and eliminates
the need for separate storage in system memory.
2 Transmit FIFO reset:
1: Bytes in receiver FIFO and counter are
reset. Shift register is not reset (bit is self-
clearing)
0: No effect 0 LPC: w
3 Receiver/Transmitter ready. Not supported. 0 LPC: w
5:4 Reserved 0 LPC: w
7:6 Receiver FIFO interrupt trigger level:
00: 1 byte
01: 4 bytes
10: 8 bytes
11: 14 bytes 0 LPC: w
Table 6-34 FIFO Control Register (FCR) (continued)
LPC IO Address: Base + 2
Bit Description Default Access
Table 6-35 Line Control Register (LCR)
LPC IO Address: Base + 3
Bit Description Default Access
1:0 Serial character WORD length:
00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits 0 LPC: r/w