Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 142)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 142
In non-FIFO mode, three of the LSR register bits, parity error, framing error, and break
interrupt, show the error status of the character that has been received. In FIFO mode, these
three bits of status are stored with each received character in the FIFO. LSR shows the status
bits of the character at the top of the FIFO. When the character at the top of the FIFO has errors,
the LSR error bits are set and are not cleared until software reads LSR, even if the character in
the FIFO is read and a new character is now at the top of the FIFO.
Bits one through four are the error conditions that produce a receiver line status interrupt when
any of the corresponding conditions are detected and the interrupt is enabled. These bits are
not cleared by reading the erroneous byte from the FIFO or receive buffer.
They are cleared only by reading LSR. In FIFO mode, the line status interrupt occurs only when
the erroneous byte is at the top of the FIFO. If the erroneous byte being received is not at the
top of the FIFO, an interrupt is generated only after the previous bytes are read and the
erroneous byte is moved to the top of the FIFO.
Table 6-37 Line Status Register (LSR)
LPC IO Address: Base + 5
Bit Description Default Access
0 Receiver data ready indicator
DR is set whenever a complete incoming
character has been received and transferred
into the RBR or the FIFO. DR is cleared by
reading all of the data in the RBR or the FIFO:
1: New data received
0: No new data 0 LPC: r