Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 165)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 165
6.3.12.11 IPMC Watchdog Timeout for OS Register
When the corresponding bits in IPMC Watchdog Timeout Register changes from 0 to 1, this
register will have its bits set to 1. The OS software can clear certain bits by writing 1 to it.
This register is only used for communication between the IPMC and the OS software. FPGA will
not use these bits by itself. BIOS should never write to this register.
6.3.12.12 FPGA-Payload-Watchdog Threshold Register
The payload software writes to this register to set the timeout threshold of a 16-bit internal
watchdog reserved for future payload use. Unit is one msec, with a maximum time of 65535
ms. When "0" is written into it, the watchdog will be disabled and will never bite.
Table 6-62 IPMC Watchdog Timeout for OS Register
Address Offset: 0x19
Bit Description Default Access
0 IPMC Watchdog Timeout
1: IPMC Watchdog Timeout occurred 0 LPC: r/w1c
1 IPMC Watchdog Pre-Timeout
1: IPMC Watchdog Pre-Timeout occurred 0 LPC: r/w1c
7:2 Reserved 000000 LPC: r
Watchdog will be cleared each time when writing new threshold registers.
Watchdog will be cleared during power-up reset and cold reset.
Table 6-63 FPGA-Payload-Watchdog Threshold Low-byte Register
Address Offset: 0x1A
Bit Description Default Access
7:0 Low byte of timeout threshold for FPGA-
Payload-Watchdog, unit is one msec 0xFF LPC: r/w