Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 147)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 147
2 Trailing Edge Ring indicator (TERI) detector
TERI indicates that the RI# input to the chip
has changed from low level to high level.
When TERI is set and the modem status
interrupt is enabled, a modem status
interrupt is generated. Not supported. 0 LPC: r/w
3 Change in Delta Data Carrier Detect (DDCD)
indicator
DDCD indicates that the DCD# input to the
chip has changed state since the last time it
was read by the CPU. When DDCD is set and
the modem status interrupt is enabled, a
modem status interrupt is generated. Not
supported. 0 LPC: r/w
4 Complement of the clear-to-send (CTS#)
input
When the ACE is in diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the
MCR bit 1 (RTS#). Ext. LPC: r
5 Complement of the data set ready (DSR#)
input
When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the
MCR bit 0 (DTR#). Ext. LPC: r
6 Complement of the ring indicator (RI#) input
When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the
MCR bit 2 (OUT1#). Not supported. Ext. LPC: r
7 Complement of the data carrier detect
(DCD#) input
When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the
MCR bit 3 (OUT2#). Not supported. Ext. LPC: r
Table 6-38 Modem Status Register (MSR) (continued)
LPC IO Address: Base + 6
Bit Description Default Access