Artesyn ATCA 7370 / ATCA 7370-S Installation and Use (January 2015) - Manual (Page 135)

Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54H) 135
6.2.5.4 Interrupt Identification Register (IIR)
In order to minimize software overhead during data character transfers, UART prioritizes
interrupts into four levels and records these in the IIR. The IIR stores information indicating that
a prioritized interrupt is pending, as well as the source of that interrupt. The four levels are listed
in the succeeding table.
3 Modem status interrupt enable/disable:
1: modem status interrupt enabled
0: modem status interrupt disabled 0 LPC :r/w
7:4 Reserved 0 LPC: r
Table 6-30 Interrupt Enable Register (IER) if DLAB=0 (continued)
LPC IO Address: Base + 1
Bit Description Default Access
Table 6-31 UART Interrupt Priorities
Priority Level Interrupt Source
1 (highest) Receiver Line Status. One or more error bits were set.
2 Received Data is available. In FIFO mode, trigger level was reached; in non-FIFO
mode, RBR has data.
2 Receiver Time out occurred. It happens in FIFO mode only, when there is data in the
receive FIFO but no activity for a time period.
3 Transmitter requests data. In FIFO mode, the transmit FIFO is half or more than half
empty; in non-FIFO mode, THR is read already
4 Modem Status: one or more of the modem input signals has changed state
Table 6-32 Interrupt Identification Register (IIR)
LPC IO Address: Base + 2
Bit Description Default Access
0 Interrupt status bit:
1: no interrupt pending
0: interrupt pending 1 LPC: r