Altera V-Series Avalon-MM DMA User Manual
User guide
Table of contents
Document Outline
- V-Series V-Series Avalon-MM DMA Interface for PCIe SolutionsUser Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Avalon-MM DMA
- Generating the Testbench
- Simulating the Example Design in ModelSim
- Running a Gate-Level Simulation
- Generating Quartus II Synthesis Files
- Creating a Quartus II Project
- Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
- Compiling the Design
- Descriptor Controller Connectivity when Instantiated Separately
- 3. Parameter Settings
- 4. Interfaces and Signal Descriptions
- V-Series DMA Avalon-MM DMA Interface to the Application Layer
- Clock Signals
- Reset, Status, and Link Training Signals
- MSI Interrupts for Endpoints
- Physical Layer Interface Signals
- Transceiver Reconfiguration
- Serial Data Signals
- Physical Layout of Hard IP In Arria V GX/GX/SX/ST Devices
- Channel Placement in Arria V Devices
- Physical Layout of Hard IP in Cyclone V Devices
- Channel Placement in Cyclone V Devices
- Physical Layout of Hard IP in Arria V GZ Devices
- Physical Layout of Hard IP in Stratix V GX/GT/GS Devices
- Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
- PIPE Interface Signals
- Test Signals
- 5. Registers
- Correspondence between Configuration Space Registers and the PCIe Specification
- Type 0 Configuration Space Registers
- PCI Express Capability Structures
- Altera-Defined VSEC Registers
- CvP Registers
- Uncorrectable Internal Error Mask Register
- Uncorrectable Internal Error Status Register
- Correctable Internal Error Mask Register
- Correctable Internal Error Status Register
- DMA Descriptor Controller Registers
- Control Register Access (CRA) Avalon-MM Slave Port
- 6. Reset and Clocks
- 7. Error Handling
- 8. IP Core Architecture
- 9. Transceiver PHY IP Reconfiguration
- A. Transaction Layer Packet (TLP) Header Formats
- B. Additional Information