Altera V-Series Avalon-MM DMA User Manual

Page 4

• Extended credit allocation settings to better optimize the RX buffer space based on application type.

• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error

reporting (AER) for high reliability applications.

• Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space

and support multiple functions.

• Support for Gen3 PIPE simulation.

• Support for V-Series Avalon-MM DMA for PCI Express with either a 128- or 256-bit interface to the

Application Layer. This variant includes an embedded DMA controller for data transfers. The

following table shows the available configurations.

Configuration

Available Devices

Interface

Width

Application Layer

Clock Frequency

Gen1 x8

Arria

V, Arria V GZ, Stratix

128 bits

125 MHz

Gen2 x4

Arria V, Arria V GZ, Cyclone,

V Stratix V

128 bits

125 MHz

Gen2 x8

Arria V GZ, Stratix V

128 bits

250 MHz

Gen2 x8

Arria V GZ, Stratix V

256 bits

125 MHz

Gen3 x4

Arria V GZ, Stratix V

128 bits

250 MHz

Gen3 x4

Arria V GZ, Stratix V

256 bits

125 MHz

Gen3 x8

Arria V GZ, Stratix V

256 bits

250 MHz

• Easy to use:

• Flexible configuration.

• No license requirement.

• Example designs to get started.

Table 1-2: Feature Comparison for all Hard IP for PCI Express IP Cores

The table compares the features of the four Hard IP for PCI Express IP Cores.

Feature

Avalon‑ST Interface

Avalon‑MM

Interface

Avalon‑MM DMA

Avalon‑ST Interface with SR-

IOV

IP Core License Free

Free

Native

Endpoint

Supported

Legacy

Endpoint

(1)

Supported

Not Supported

Root port

Supported

Not Supported

Gen1

×1, ×2, ×4, ×8

Not Supported

×8

(1)

Not recommended for new designs.

UG-01154

2014.12.18

Features

1-3

Datasheet

Altera Corporation

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