Altera V-Series Avalon-MM DMA User Manual
Page 58
Figure 4-12: Cyclone V GX/GT/ST/ST Devices with 9 or 12 Transceiver Channels and 2 PCIe Cores
In the following figure, the Hard IP for PCI Express uses channel 1 and channel 2 of GXB_L0 and channel
1 and channel 1 of GXB_L2.
GXB_L0
PCIe
Hard IP
Ch 2
Ch 1
Ch 0
Ch 2
Ch 1
Ch 0
5CGXC9
GXB_L1
PCIe
Hard IP
Devices Available
Number of Channels Per Bank
Transceiver Bank Names
Ch 2
Ch 1
Ch 0
Ch 2
Ch 1
Ch 0
GXB_L2
GXB_L3
Figure 4-13: Cyclone V GX/GT/ST/ST Devices with 6 Transceiver Channels and 2 PCIe Cores
GXB_L0
PCIe
Hard IP
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
Ch 0
5CGXC4
5CGXC5
PCIe
Hard IP
Devices Available
Number of Channels Per Bank
Transceiver Bank Names
GXB_L1
For more comprehensive information about Cyclone V transceivers, refer to the Transceiver Banks
section in the Transceiver Architecture in Cyclone V Devices.
Related Information
UG-01154
2014.12.18
Physical Layout of Hard IP in Cyclone V Devices
4-27
Interfaces and Signal Descriptions
Altera Corporation
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