Altera V-Series Avalon-MM DMA - Manual (Page 67)

Signal Direction Description
txcompl0
Output Transmit compliance . This signal forces the running
disparity to negative in compliance mode (negative COM
character).
txdata0[31:0] Output Transmit data. This bus transmits data on lane .
txdatak0[3:0] Output Transmit data control . This signal serves as the control bit
for
txdata
. Bit 0 corresponds to the lowest-order byte of
rxdata
, and so on. A value of 0 indicates a data byte. A value of 1
indicates a control byte. For Gen1 and Gen2 only.
txdataskip0 Output For Gen3 operation. Allows the MAC to instruct the TX interface
to ignore the TX data interface for one clock cycle. The following
encodings are defined:
• 1’b0: TX data is invalid
• 1’b1: TX data is valid
txdeemph0 Output Transmit de-emphasis selection. The value for this signal is set
based on the indication received from the other end of the link
during the Training Sequences (TS). You do not need to change
this value.
txdetectrx0
Output Transmit detect receive . This signal tells the PHY layer to
start a receive detection operation or to begin loopback.
txelecidle0
Output Transmit electrical idle . This signal forces the TX output to
electrical idle.
tx_margin0[2:0]
Output Transmit V
OD
margin selection. The value for this signal is based
on the value from the
Link Control 2 Register
. Available for
simulation only.
txswing0 Output When asserted, indicates full swing for the transmitter voltage.
When deasserted indicates half swing.
txsynchd0[1:0] Output For Gen3 operation, specifies the block type. The following
encodings are defined:
• 2'b01: Ordered Set Block
• 2'b10: Data Block
4-36 PIPE Interface Signals
UG-01154
2014.12.18
Altera Corporation Interfaces and Signal Descriptions
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