Altera V-Series Avalon-MM DMA User Manual
Page 99
Byte Offset
Register
Dir
Description
14'h006C
lane_act_reg[3:0]
O
Lane Active Mode: This signal indicates the number
of lanes that configured during link training. The
following encodings are defined:
• 4’b0001: 1 lane
• 4’b0010: 2 lanes
• 4’b0100: 4 lanes
• 4’b1000: 8 lanes
Related Information
•
•
5-30
Control Register Access (CRA) Avalon-MM Slave Port
UG-01154
2014.12.18
Altera Corporation
Registers
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