Altera V-Series Avalon-MM DMA - Manual (Page 42)

Bits Name Description
[153:14
6]
DMA Descriptor ID Specifies up to 128 descriptors.
[159:15
4]
Reserved —
DMA Descriptor Status Bus when Instantiated Separately
Read DMA and Write DMA modules report status to the Descriptor Controller on the
RdDmaTx-
Data_o[31:0]
or
WrDmaTxData_o[31:0]
bus when one of the following trigger events occurs:
• A descriptor is activated
• A descriptor completes successfully
The following table shows the mappings of the triggering events to the DMA descriptor status bus:
Table 4-11: DMA Status Bus
Bits Name Description
[31:9] Reserved. —
[8] Done When asserted, a single DMA descriptor has completed success‐
fully.
[7:0]
Descriptor ID
The ID of the descriptor whose status is being reported.
Descriptor Controller Interfaces when Instantiated Internally
Read Descriptor Controller Avalon-MM Master Port
The Read Descriptor Controller Avalon-MM master port drives the TX Avalon-MM slave port. This port
drives single dword transactions to the V-Series Avalon-MM DMA for PCIe. The Read Descriptor
Controller uses this port to write descriptor status to the PCIe domain and possibly to MSI when MSI
messages are enabled.
Table 4-12: Read Descriptor Controller Avalon-MM Master Interface
Signal Name Direction Description
RdDCMAddress_o[63:0] Output Specifies the address for the read data.
RdDCMByteEnable_
o[3:0]
Output Specifies which data bytes are valid.
RdDCMReadDataValid_i Input When asserted, indicates that the read data is valid.
RdDCMReadData_o[31:0] Output
Drives the single dword read data.
UG-01154
2014.12.18
DMA Descriptor Status Bus when Instantiated Separately 4-11
Interfaces and Signal Descriptions Altera Corporation
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