Altera V-Series Avalon-MM DMA - Manual (Page 90)

Read DMA and Write DMA Descriptor Format
Read and write descriptors are stored in separate descriptor tables. Each table can store up to 128 descrip‐
tors. Each descriptor is 8 dwords, or 32 bytes. The Read DMA and Write DMA descriptor tables start at a
0x200 byte offset from the addresses programmed into the
RC Read Descriptor Base
and
RC Write
Descriptor Base
address registers.
Table 5-17: Read Descriptor Format
Address
Offset
Register Name
Description
0x00 RD_RC_LOW_SRC_ADDR Lower dword of the read DMA source address. Specifies
the address in Root Complex memory from which the
Read DMA fetches data.
0x04 RD_RC_HIGH_SRC_ADDR Upper dword of the read DMA source address. Specifies
the address in Root Complex memory from which the
Read DMA fetches data.
0x08 RD_CTLR_LOW_DEST_ADDR Lower dword of the read DMA destination address.
Specifies the address in the Avalon-MM domain to
which the Read DMA writes data.
0x0C RD_CTRL_HIGH_DEST_ADDR Upper dword of the read DMA destination address.
Specifies the address in the Avalon-MM domain to
which the Read DMA writes data.
0x10
CONTROL
Specifies the following information:
• [31:25] Reserved must be 0.
• [24:18]
ID
. Specifies the
Descriptor ID
.
Descriptor
ID
0 is at the beginning of the table.
Descriptor ID
is at the end of the table.
• [17:0]
SIZE
. The transfer size in dwords. Must be
non-zero. The maximum transfer size in 1 MBytes -
4 bytes.
0x14 -
0x1C
Reserved N/A
Table 5-18: Write Descriptor Format
Address
Offset
Register Name
Description
0x00 WR_RC_LOW_SRC_ADDR Lower dword of the write DMA source address.
Specifies the address in the Avalon-MM domain from
which the Write DMA fetches data.
UG-01154
2014.12.18
Read DMA and Write DMA Descriptor Format 5-21
Registers Altera Corporation
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