Altera V-Series Avalon-MM DMA - Manual (Page 34)

Figure 4-2: Signals When DMA Descriptor Controller Is Instantiated Externally
tx_out0[-1:0]
rx_in0[-1:0]
Hard IP Serial
Hard IP for PCI Express Using Avalon-MM with DMA
TxsWriteData_i[31:0]
TxsRead_i
TxsWrite_i
TxsChipSelect_i
TxsAddress_i[-1:0]
TxsByteEnable[3:0]
TxsReadData_o[31:0]
TxsReadDataValid_o
TxsWaitRequest_o
TX Slave:
Allows FPGA to send single
dword reads or writes
from FPGA to Root Port
RxmRead_o
RxmWrite_o
RxmAddress_o[-1:0]
RxmBurstCount_o[5:0]
RxmByteEnable_o[3:0]
RxmWriteData_o[31:0]
RxmReadData_i[31:0]
RxmReadDataValid_i
RxmWaitRequest_i
CraWriteData_o[31:0]
CraWaitRequest_o
CraChipSelect_i
CraByteEnable_i[3:0]
CraAddress_i[13:0]
CraRead
CraWrite
CraReadData[31:0]
Local Avalon-MM or
Host Access to
Control/Status Regs
of Avalon-MM Bridge
MsiIntfc_o[81:0]
MSIxIntfc_o[15:0]
RdDmaWrite_o
RdDmaAddress_o[63:0]
RdDmaWriteData[-1:0]
RdDmaBurstCount_o[-1:0]
RdDmaWriteEnable_o[-1:0]
RdDmaWaitRequest_i
DMA Read Avalon-MM :
Writes data from Host
memory to FPGA memory.
WrDmaRead_o
WrDmaAddress_o[63:0]
WrDmaReadData_i[-1:0]
WrDmaBurstCount_o[-1:0]
WrDmaWaitRequest_i
WrDmaReadDataValid_i
DMA Write Avalon-MM :
Fetch data from FPGA memory
before sending to Host memory.
MSI and MSI-X
Interface
npor
reset_status
pin_perst
Reset &
Lock Status
Clocks refclk
coreclkout
= 32 or 64 Avalon-MM Master
for Host to access
registers and memory
1 RX Master for each
BAR
cfg_par_err
derr_cor_ext_rcv
derr_cor_ext_rpl
derr_rpl
dlup
dlup_exit
ev128ns
ev1us
hotrst_exit
int_status[3:0]
ko_cpl_spc_data[11:0]
ko_cpl_spc_header[7:0]
l2_exit
lane_act[3:0]
ltssmstate[4:0]
rx_par_err
tx_par_err
Hard IP Reset,
Status and
Link Training
Hard IP Control &
Current Speed
Interfaces
test_in[31:0]
simu_mode_pipe
current_speed[1:0]
tl_cfg_add[3:0]
tl_cfg_ctl[31:0]
tl_cfg_sts[52:0]
PIPE
(simulation
only)
reconfig_from_xcvr[46-1:0]
reconfig_to_xcvr[70-1:0]
reconfig_clk_locked
Transaction Layer
Transceiver
Reconfiguration
Configuration
eidleinfersel0[2:0]
phystatus0
powerdown0[1:0]
rxdata0[31:0]
rxdatak0
rxelecidle0
rxpolarity
rxstatus0[2:0]
rxvalid0
sim_ltssmstate[4:0]
sim_pipe_pclk_in
sim_pipe_rate[1:0]
txcompl0
txdata[-1:0]
txdatak0
txdeemph0
txdetectrx0
txelecidle0
txmargin0
txswing
Host or
RdDmaRxData_i[159:0]
RdDmaRxValid_i
RdDmaRxReady_o
WrDmaRxData_i[159:0]
WrDmaRxValid_i
WrDmaRxReady_o
WrDmaTxData_o[31:0]
WrDmaTxValid_o
Descriptor Instructions
from
Descriptor Controller
to DMA Engine
RdDmaTxData_o[31:0]
RdDmaTxValid_o
Read DMA Avalon-MM Master Port
The Read DMA module sends memory read TLPs upstream. It writes the completion data to an external
Avalon-MM interface through the high throughput Read Master port. This port operates on descriptors
the IP core receives from the DMA Descriptor Controller.
UG-01154
2014.12.18
Read DMA Avalon-MM Master Port 4-3
Interfaces and Signal Descriptions Altera Corporation
Send Feedback