Altera V-Series Avalon-MM DMA User Manual
Page 137
Date
Version
Changes Made
2014.08.18
14.0 Arria 10
Made the following changes to the V-Series Avalon-MM DMA for
PCI Express IP core:
• Revised programming model for the Descriptor Controller.
• Added simulation log file,
altpcie_monitor_a10_dlhip_tlp_file_log.log
,
that is automatically generated in your simulation directory. To
simulate in the Quartus II 14.0 software release, you must
regenerate your IP core to create the supporting monitor file the
generates
altpcie_monitor_a10_dlhip_tlp_file_log.log
. Refer to
Understanding Simulation Dump File Generation for details.
• Added support for either 128- or 256-bit interface to the Applica‐
tion Layer.
• Added support for 64-bit addressing, making address translation
unnecessary.
• Removed Channel Placement for PCIe in Arria 10 Devices. Please
contact your Altera sales representative for PLL and channel
usage.
• Added support for optional bursting RX Master for BAR2.
• Revised Read DMA Example and Software Program for Simulta‐
neous Read and Write DMA to work with revised programming
model for the Descriptor Controller.
• Added the following optimizations for the Descriptor Controller:
• Optimized performance for smaller payloads such as 64-byte
Ethernet packets
• Reduced overhead for host updates
• Support for concurrent dynamic host updates and DMA
operation
• Support for choice to embed Descriptor Controller in the
Avalon-MM bridge or instantiate separately
• Added access to selected Configuration Space registers and link
status registers through the optional Control Register Access
(CRA) Avalon-MM slave port.
• Added simulation support for Phase 2 and Phase 3 equalization
when requested by third-party BFM for Gen3 variants.
• Added multiple MSI/MSI-X support.
B-2
Revision History for the Avalon-MM Interface with DMA
UG-01154
2014.12.18
Altera Corporation
Additional Information