Altera V-Series Avalon-MM DMA - Manual (Page 36)

Write DMA Avalon-MM Master Port
The Write DMA module fetches data from the Avalon-MM address space using this interface before
issuing memory write requests to transfer data to host memory.
Table 4-2: DMA Read 256-Bit Avalon-MM Master Interface
Signal Name Direction Description
WrDmaRead_o Output When asserted, indicates that the Write DMA module
reading data from a memory component in the
Avalon-MM address space to write to the PCIe address
space.
WrDmaAddress_o[63:0] Output Specifies the address for the data to be read from a
memory component in the Avalon-MM address space .
WrDmaReadData_i[127 or
255:0]
Input Specifies the completion data that will be written to the
PCIe address space by the Write DMA module.
WrDmaBurstCount_
o[4:0]or[5:0]
Output Specifies the burst count in 128- or 256-bit words. This
bus is 5 bits for the 256-bit interface. It is 6 bits for the
128-bit interface
WrDmaWaitRequest_i Input When asserted, indicates that the memory is not ready to
be read.
WrDmaReadDataValid_i Input When asserted, indicates that
WrDmaReadData_i
is valid.
Figure 4-4: Write DMA Avalon-MM Master Reads Data from FPGA Memory
\write_data_mover.\WrDmaAddress_o[63:0]
\write_data_mover\WrDmaBurstCount_o[4:0]
\write_data_mover.\WrDmaRead_o
\write_data_mover.\WrDmaWaitRequest_i
\write_data_mover\.WrDmaReadDataValid_i
\write_data_mover.\WrDmaReadData_i[255:0]
100 180 200 280 300 380 400 480 500
RX Master Module
The RX Master module translates read and write TLPs received from the PCIe link to Avalon-MM
requests for Qsys components connected to the interconnect. This module allows other PCIe
components, including host software, to access other Avalon-MM slaves connected in the Qsys system.
UG-01154
2014.12.18
Write DMA Avalon-MM Master Port 4-5
Interfaces and Signal Descriptions Altera Corporation
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