Features – Altera V-Series Avalon-MM DMA User Manual
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Table 1-1: PCI Express Data Throughput
The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 2, 4, and 8
lanes. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and
8.0 giga-transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive (RX)
channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20%
overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to less
than 1%.
Link Width in Gigabits Per Second (Gbps)
×2
×4
×8
PCI Express Gen1 (2.5 Gbps)
N/A
N/A
16
PCI Express Gen2 (5.0 Gbps)
8
16
32
PCI Express Gen3 (8.0 Gbps)
15.75
31.51
63
Related Information
•
•
•
Features
New features in the Quartus
®
II 14.1 software release:
• New PCI Express Multi-Channel DMA Interface IP Core to demonstrate multi-channel operation.
This component is available in the Qsys IP Catalog under Interface Protocols > PCI Express > Qsys
Example Designs
• New Avalon-MM DMA FIFO Mode IP Core for PCI Express to provide a FIFO interface to the Data
Mover included in the Avalon-MM bridge. This component is available in the Qsys IP Catalog under
Interface Protocols > PCI Express > Qsys Example Designs
• Support for 128-Bit Avalon-MM RX master.
• Reduced Quartus II compilation warnings by 50%.
The V-Series Avalon-MM DMA for PCI Express supports the following features:
• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as
hard IP.
• Native support for Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x4, Gen3 x8 for Endpoints. The variant
downtrains when plugged into a lesser link width or changes to a different maximum link rate.
• Dedicated 16 KByte receive buffer.
• Optional hard reset controller for Gen2.
• Support for 128- or 256-bit Avalon-MM interface to Application Layer with embedded DMA up to
Gen3 ×8 data rate.
• Support for 32- or 64-bit addressing for the Avalon-MM interface to the Application Layer.
• Qsys example designs demonstrating parameterization, design modules, and connectivity.
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Features
UG-01154
2014.12.18
Altera Corporation
Datasheet