Altera V-Series Avalon-MM DMA User Manual
Page 25
Parameter
Value
Description
Reference clock
frequency
100 MHz
125 MHz
The PCI Express Base Specification 3.0 requires a
100 MHz ±300 ppm reference clock. The 125 MHz reference
clock is provided as a convenience for systems that include a
125 MHz clock source. For more information about Gen3
operation, refer to 4.3.8 Refclk Specifications for 8.0 GT/s in the
specification.
For Gen3 operation, Altera recommends using a common
reference clock (0 ppm) because when using separate
reference clocks (non 0 ppm), the PCS occasionally must
insert SKP symbols, potentially causes the PCIe link to go to
recovery. Gen1 or Gen2 modes are not affected by this issue.
Systems using the common reference clock (0 ppm) are not
affected by this issue. The primary repercussion of this is a
slight decrease in bandwidth. On Gen3 x8 systems, this
bandwidth impact is negligible. If non 0 ppm mode is
required, so that separate reference clocks are being used,
please contact Altera for further information and guidance.
Instantiate
internal
descriptor
controller
On/Off
When you turn this option on, the descriptor controller is
included in the Avalon-MM bridge. When you turn this
option off, the descriptor controller should be included as a
separate external component. Turn this option on, if you plan
to use the Altera-provided descriptor controller in your
design. Turn this option off if you plan to modify or replace
the descriptor controller logic in your design.
Enable Avalon-
MM CRA Slave
hard IP status
port
On/Off
Allows read and write access to bridge registers from the
interconnect fabric using a specialized slave port. This option
is required for Requester/Completer variants and optional for
Completer Only variants. Enabling this option allows read
and write access to bridge registers, except in the Completer-
Only single dword variations.
Enable burst
capabilities for
RXM BAR2 port
On/Off
When you turn on this option, the BAR2 RX Avalon-MM
masters is burst capable. If BAR2 is 32 bits and Burst capable,
then BAR3 is not available for other use. If BAR2 is 64 bits, the
BAR3 register holds the upper 32 bits of the address.
Enable configu‐
ration via the
PCIe link
On/Off
On, the Quartus II software places the Endpoint in the
location required for configuration via protocol (CvP). For
more information about CvP, click the Configuration via
Protocol (CvP) link below
3-4
System Settings
UG-01154
2014.12.18
Altera Corporation
Parameter Settings