Altera V-Series Avalon-MM DMA - Manual (Page 10)

Compatibility Testing Environment
Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera
internally tests every release with motherboards and PCI Express switches from a variety of manufac‐
turers. All PCI-SIG compliance tests are run with each IP core release.
Performance and Resource Utilization
Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device
resources.
The V-Series variants include a soft logic bridge that functions as a front end to the hardened protocol
stack. The following table shows the typical expected device resource utilization for selected configura‐
tions using the current version of the Quartus II software targeting a V-Series device. With the exception
of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 50.
Table 1-5: Performance and Resource Utilization V-Series Avalon-MM DMA for PCI Express
Interface Width ALMs M20K Memory Blocks Logic Registers
128 1100 14 1650
256 1750 19 2600
Note: Soft calibration of the transceiver module requires additional logic. The amount of logic required
depends upon the configuration.
Related Information
Fitter Resources Reports
V-Series Recommended Speed Grades
Altera recommends setting the Quartus II Analysis & Synthesis Settings Optimization Technique to
Speed when the Application Layer clock frequency is 250 MHz. For information about optimizing
synthesis, refer to Setting Up and Running Analysis and Synthesis in Quartus II Help. For more informa‐
tion about how to effect the Optimization Technique settings, refer to Area and Timing Optimization in
volume 2 of the Quartus II Handbook. .
UG-01154
2014.12.18
Compatibility Testing Environment 1-9
Datasheet Altera Corporation
Send Feedback