Altera V-Series Avalon-MM DMA - Manual (Page 26)

Parameter Value Description
Use ATX PLL
On/Off When you turn on this option, the Hard IP for PCI Express
uses the ATX PLL instead of the CMU PLL. For other configu‐
rations, using the ATX PLL instead of the CMU PLL reduces
the number of transceiver channels that are necessary. This
option requires the use of the soft reset controller and does not
support the CvP flow.
Enable Hard IP
reset pulse at
power-up when
using the soft
reset controller
On/Off
When you turn on this option, the soft reset controller
generates a pulse at power up to reset the Hard IP. This pulse
ensures that the Hard IP is reset after programming the
device, regardless of the behavior of the dedicated PCI Express
reset pin,
perstn
. This option is available for Gen2 and Gen3
designs that use a soft reset controller.
Base Address Register (BAR) Settings
The type and size of BARs available depend on port type.
Table 3-2: BAR Registers
Parameter Value Description
Type Disabled
64-bit prefetchable memory
32-bit non-prefetchable memory
32-bit prefetchable memory
I/O address space If you select 64-bit prefetchable memory, 2
contiguous BARs are combined to form a 64-bit
prefetchable BAR; you must set the higher numbered
BAR to Disabled.
Defining memory as prefetchable allows contiguous
data to be fetched ahead. Prefetching memory is
advantageous when the requestor may require more
data from the same region than was originally
requested. If you specify that a memory is prefetch‐
able, it must have the following 2 attributes:
• Reads do not have side effects
• Write merging is allowed
The 32-bit prefetchable memory and I/O address
space BARs are only available for the Legacy
Endpoint.
Size
N/A Qsys automatically calculates the required size after
you connect your components.
UG-01154
2014.12.18
Base Address Register (BAR) Settings 3-5
Parameter Settings Altera Corporation
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