Running a gate-level simulation, Generating quartus ii synthesis files, Creating a quartus ii project – Altera V-Series Avalon-MM DMA User Manual
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The
ld_debug
command compiles all design files and elaborates the top-level design without any
optimization.
c.
run -all
The simulation performs the following operations:
• Various configuration accesses after the link is initialized
• Setup of the DMA controller to read data from the Transaction Layer Direct BFM’s shared memory
• Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM’s shared
memory
• Data comparison and report of any mismatch
Running a Gate-Level Simulation
The PCI Express testbenches run simulations at the register transfer level (RTL). However, it is possible to
create you own gate-level simulations. Contact your Altera Sales Representative for instructions and an
example that illustrate how to create a gate-level simulation from the RTL testbench.
Generating Quartus II Synthesis Files
1. On the Generate menu, select Generate HDL.
2. For Create HDL design files for synthesis, select Verilog.
You can leave the default settings for all other items.
3. Click Generate to generate files for Quartus II synthesis.
4. Click Finish when the generation completes.
Creating a Quartus II Project
You can create a new Quartus II project with the New Project Wizard, which helps you specify the
working directory for the project, assign the project name, and designate the name of the top-level design
entity.
1. On the Quartus II File menu, click then New Project Wizard, then Next.
2. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you
previously turned it off.)
3. On the Directory, Name, Top-Level Entity page, enter the following information:
a. For What is the working directory for this project, browse to
integrated/
.
b. For What is the name of this project? browse to the
synthesis
directory and select
pcie_de_ep_dma_g3x8_integrated.v
.
c. Click Next.
4. For Project Type select Empty project.
5. Click Next.
6. On the Add Files page, add
integrated.qip
to your Quartus II project.
7. Click Next to display the Family & Device Settings page.
UG-01154
2014.12.18
Running a Gate-Level Simulation
2-5
Getting Started with the Avalon-MM DMA
Altera Corporation