Type 0 configuration space registers – Altera V-Series Avalon-MM DMA User Manual
Page 74
Byte Address
Hard IP Configuration Space Register
Corresponding Section in PCIe Specification
0x818
Advanced Error Capabilities and Control
Register
Advanced Error Capabilities and Control
Register
0x81C
Header Log Register
Header Log Register
0x82C
Root Error Command
Root Error Command Register
0x830
Root Error Status
Root Error Status Register
0x834
Error Source Identification Register Correct‐
able Error Source ID Register
Error Source Identification Register
Related Information
Type 0 Configuration Space Registers
Figure 5-1: Type 0 Configuration Space Registers - Byte Address Offsets and Layout
Endpoints store configuration data in the Type 0 Configuration Space. The
Configuration Space Registers and the PCIe Specification
on page 5-1 lists the appropriate section of
the PCI Express Base Specification that describes these registers.
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
Device ID
Vendor ID
Status
Command
Class Code
Revision ID
0x00
Header Type
0x00
Cache Line Size
BAR Registers
BAR Registers
BAR Registers
BAR Registers
BAR Registers
BAR Registers
Reserved
Subsystem Device ID
Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Reserved
Capabilities Pointer
0x00
Interrupt Pin
Interrupt Line
31
24 23
16 15
8 7
0
UG-01154
2014.12.18
Type 0 Configuration Space Registers
5-5
Registers
Altera Corporation