Pci express capability structures – Altera V-Series Avalon-MM DMA User Manual
Page 75
PCI Express Capability Structures
Figure 5-2: MSI Capability Structure
0x050
0x054
0x058
Message Control
Configuration MSI Control Status
Register Field Descriptions
Next Cap Ptr
Message Address
Message Upper Address
Reserved
Message Data
31
24 23
16 15
8 7
0
0x05C
Capability ID
Figure 5-3: MSI-X Capability Structure
0x068
0x06C
0x070
Message Control
Next Cap Ptr
MSI-X Table Offset
MSI-X Pending Bit Array (PBA) Offset
31
24 23
16 15
8 7
0
Capability ID
3 2
MSI-X
Table BAR
Indicator
MSI-X
Pending
Bit Array
- BAR
Indicator
Figure 5-4: Power Management Capability Structure - Byte Address Offsets and Layout
0x078
0x07C
Capabilities Register
Next Cap Ptr
Data
31
24 23
16 15
8 7
0
Capability ID
Power Management Status and Control
PM Control/Status
Bridge Extensions
5-6
PCI Express Capability Structures
UG-01154
2014.12.18
Altera Corporation
Registers
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)