Altera V-Series Avalon-MM DMA - Manual (Page 50)

Signal Direction Description
• 00110: config.Linkwidthstart
• 00111: Config.Linkaccept
• 01000: Config.Lanenumaccept
• 01001: Config.Lanenumwait
• 01010: Config.Complete
• 01011: Config.Idle
• 01100: Recovery.Rcvlock
• 01101: Recovery.Rcvconfig
• 01110: Recovery.Idle
• 01111: L0
• 10000: Disable
• 10001: Loopback.Entry
• 10010: Loopback.Active
• 10011: Loopback.Exit
• 10100: Hot.Reset
• 10101: L0s
• 11001: L2.transmit.Wake
• 11010: Speed.Recovery
• 11011: Recovery.Equalization, Phase 0
• 11100: Recovery.Equalization, Phase 1
• 11101: Recovery.Equalization, Phase 2
• 11110: recovery.Equalization, Phase 3
rx_par_err Output When asserted for a single cycle, indicates that a parity error was
detected in a TLP at the input of the RX buffer. This error is
logged as an uncorrectable internal error in the VSEC registers.
For more information, refer to Uncorrectable Internal Error
Status Register. You must reset the Hard IP if this error occurs
because parity errors can leave the Hard IP in an unknown state.
The signal is not available for Arria V and Cyclone V devices.
tx_par_err[1:0] Output When asserted for a single cycle, indicates a parity error during
TX TLP transmission. These errors are logged in the VSEC
register. The following encodings are defined:
• 2’b10: A parity error was detected by the TX Transaction
Layer. The TLP is nullified and logged as an uncorrectable
internal error in the VSEC registers. For more information,
refer to Uncorrectable Internal Error Status Register.
• 2’b01: Some time later, the parity error is detected by the TX
Data Link Layer which drives 2’b01 to indicate the error.
Reset the IP core when this error is detected. Contact Altera
technical support if resetting becomes unworkable.
UG-01154
2014.12.18
Reset, Status, and Link Training Signals 4-19
Interfaces and Signal Descriptions Altera Corporation
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