Altera V-Series Avalon-MM DMA - Manual (Page 95)

Control Register Access (CRA) Avalon-MM Slave Port
Table 5-19: Configuration Space Register Descriptions
The optional CRA Avalon-MM slave port provides host access to selected Configuration Space and status
registers. These registers are read only. For registers that are less than 32 bits, the upper bits are unused.
Byte Offset
Register Dir Description
14'h0000
cfg_dev_ctrl[15:0] O
cfg_devctrl[15:0]
is device control for the PCI
Express capability structure.
14'h0004
cfg_dev_ctrl2[15:0] O
cfg_dev2ctrl[15:0]
is device control 2 for the
PCI Express capability structure.
14'h0008
cfg_link_ctrl[15:0] O
cfg_link_ctrl[15:0]
is the primary Link Control
of the PCI Express capability structure.
For Gen2 or Gen3 operation, you must write a 1’b1
to Retrain Link bit (Bit[5] of the
cfg_link_ctrl)
of
the Root Port to initiate retraining to a higher data
rate after the initial link training to Gen1 L0 state.
Retraining directs the LTSSM to the Recovery state.
Retraining to a higher data rate is not automatic
even if both devices on the link are capable of a
higher data rate.
14'h000C
cfg_link_ctrl2[15:0] O
cfg_link_ctrl2[31:16]
is the secondary Link
Control register of the PCI Express capability
structure for Gen2 operation.
When
tl_cfg_addr=2
,
tl_cfg_ctl
returns the
primary and secondary Link Control registers,
{cfg_link_ctrl[15:0], cfg_link_
ctrl2[15:0]}
, the primary Link Status register
contents is available on
tl_cfg_sts[46:31]
.
For Gen1 variants, the link bandwidth notification
bit is always set to 0.For Gen2 variants, this bit is set
to 1.
14'h0010
cfg_prm_cmd[15:0] O Base/Primary Command register for the PCI
Configuration Space.
14'h0014
cfg_root_ctrl[7:0] O Root control and status register of the PCI-Express
capability. This register is only available in Root
Port mode.
5-26 Control Register Access (CRA) Avalon-MM Slave Port
UG-01154
2014.12.18
Altera Corporation Registers
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