Altera V-Series Avalon-MM DMA - Manual (Page 115)

Figure 8-1: V-Series Avalon-MM DMA for PCI Express
Clock
Domain
Crossing
(CDC)
Data
Link
Layer
(DLL)
Transaction
Layer (TL)
PHYMAC
Hard IP for PCI Express DMA Read
Avalon-MM
DMA Write
Avalon-MM
Avalon-MM Master
Bridge Access
Avalon-MM Master
Host Access to
Memory
Reconfiguration
PIPE
Application
Layer
Clock & Reset
Selection
Configuration
Block
Configuration
Space
PCS PMA
Physical Layer
(Transceivers)
Configuration via PCIe Link
RX Buffer
PHY IP Core for
PCI Express (PIPE)
Avalon-MM
Bridge
with
DMA
Engine
Table 8-1: Application Layer Clock Frequencies
Lanes Gen1 Gen2 Gen3
×2
N/A
125 MHz @ 128 bits 125 MHz @ 128 bits
×4
N/A
125 MHz @ 128 bits 250 MHz @ 128 bits or
125 MHz @ 256 bits
×8 125 MHz @ 128 bits 250 MHz @ 128 bits or
125 MHz @ 256 bits 250 MHz @ 256 bits
Related Information
PCI Express Base Specification 2.1 or 3.0
8-2 IP Core Architecture
UG-01154
2014.12.18
Altera Corporation IP Core Architecture
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