Altera V-Series Avalon-MM DMA - Manual (Page 65)

Table 4-23: PIPE Interface Signals
In the following table, signals that include lane number 0 also exist for lanes 1-7. These signals are for simulation
only. For Quartus II software compilation, these pipe signals can be left floating. In Qsys, the signals that are part
of the PIPE interface have the prefix, hip_pipe. The signals which are included to simulate the PIPE interface have
the prefix, hip_pipe_sim_pipe
Signal Direction Description
eidleinfersel0[2:0] Output Electrical idle entry inference mechanism selection. The
following encodings are defined:
• 3'b0xx: Electrical Idle Inference not required in current
LTSSM state
• 3'b100: Absence of COM/SKP Ordered Set the in 128 us
window for Gen1 or Gen2
• 3'b101: Absence of TS1/TS2 Ordered Set in a 1280 UI interval
for Gen1 or Gen2
• 3'b110: Absence of Electrical Idle Exit in 2000 UI interval for
Gen1 and 16000 UI interval for Gen2
• 3'b111: Absence of Electrical idle exit in 128 us window for
Gen1
phystatus0
Input PHY status . This signal communicates completion of several
PHY requests.
powerdown0[1:0]
Output Power down . This signal requests the PHY to change its
power state to the specified state (P0, P0s, P1, or P2).
rxdata0[31:0]
Input Receive data. This bus receives data on lane .
rxdatak0[3:0] Input Data/Control bits for the symbols of receive data. Bit 0
corresponds to the lowest-order byte of
rxdata
, and so on. A
value of 0 indicates a data byte. A value of 1 indicates a control
byte. For Gen1 and Gen2 only.
rxelecidle0
Input Receive electrical idle . When asserted, indicates detection of
an electrical idle.
rxpolarity0
Output Receive polarity . This signal instructs the PHY layer to
invert the polarity of the 8B/10B receiver decoding block.
rxstatus0[2:0]
Input Receive status . This signal encodes receive status and error
codes for the receive data stream and receiver detection.
rxvalid0
Input Receive valid . This symbol indicates symbol lock and valid
data on
rxdata
and
rxdatak
.
4-34 PIPE Interface Signals
UG-01154
2014.12.18
Altera Corporation Interfaces and Signal Descriptions
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