Altera V-Series Avalon-MM DMA - Manual (Page 33)

Figure 4-1: Signals When Descriptor Controller Is Embedded in the Avalon-MM Bridge
tx_out0[-1:0]
rx_in0[-1:0]
Hard IP Serial
Hard IP for PCI Express Using Avalon-MM with DMA
TxsWriteData_i[31:0]
TxsRead_i
TxsWrite_i
TxsChipSelect_i
TxsAddress_i[-1:0]
TxsByteEnable[3:0]
TxsReadData_o[31:0]
TxsReadDataValid_o
TxsWaitRequest_o
TX Slave:
Allows FPGA to Send Single
DWord Reads or Writes
from FPGA to Root Port
RxmRead_o
RdDCMAddress_0[63:0]
RdDCMByteEnable_o[3:0]
RdDCMReadDataValid_i
RdDCMRead Data_i[31:0]
RdDCMRead_o
RdDCMWaitRequest_i
RdDCMWriteData_o[31:0]
RdDCMWrite_o
RxmWrite_o
RxmAddress_o[-1:0]
RxmBurstCount_o[5:0]
RxmByteEnable_o[3:0]
RxmWriteData_o[31:0]
RxmReadData_i[31:0]
RxmReadDataValid_i
RxmWaitRequest_i
CraWriteData_o[31:0]
CraWaitRequest_o
CraChipSelect_i
CraByteEnable_i[3:0]
CraAddress_i[13:0]
CraRead
CraWrite
CraReadData[31:0]
Host Access to
Control/Status Regs
of Avalon-MM Bridge
MsiIntfc_o[81:0]
MsixIntfc_o[15:0]
RdDmaWrite_o
RdDmaAddress_o[63:0]
RdDmaWriteData[-1:0]
RdDmaBurstCount_o[4:0]
RdDmaWriteEnable_o[-1:0]
RdDmaWaitRequest_i
Read DMA Avalon-MM :
Writes data from Host
memory to FPGA memory.
WrDmaRead_o
WrDmaAddress_o[63:0]
WrDmaReadData_i[-1:0]
WrDmaBurstCount_o[-1:0]
WrDmaWaitRequest_i
WrDmaReadDataValid_i
Write DMA Avalon-MM :
Fetch data from FPGA memory
before sending to Host memory.
MSI Interface
npor
nreset_status
pin_perst
Reset &
Lock Status
Clocks refclk
coreclkout
= 32 or 64 Avalon-MM Master
Rd Descriptor Controller
Avalon-MM Master
Drives TX Slave to
Perform Single DWord
Transactions
to the Hard IP for PCIe
for Host to Access
Registers and Memory
1 RX Master for Each
BAR
cfg_par_err
derr_cor_ext_rcv
derr_cor_ext_rpl
derr_rpl
dlup
dlup_exit
ev128ns
ev1us
hotrst_exit
int_status[3:0]
ko_clp_spc_data[11:0]
ko_cpl_spc_header[7:0]
l2_exit
lane_act[3:0]
ltssmstate[4:0]
rx_par_err
tx_par_err
Hard IP Status
Hard IP Control &
Current Speed
Interfaces
test_in[31:0]
simu_mode_pipe
current_speed[1:0]
PIPE
(simulation
only)
reconfig_from_xcvr[46-1:0]
reconfig_to_xcvr[70-1:0]
reconfig_clk_locked
Transceiver
Reconfiguration
not required for
Arria 10
eidleinfersel[2:0]
phystatus0
powerdown0[1:0]
rxdata0[31:0]
rxdatak0
rxelecidle0
rxpolarity
rxstatus0[2:0]
rxvalid0
sim_ltssmstate[4:0]
sim_pipe_pclk_in
sim_pipe_rate[1:0]
txcompl0
txdata[-1:0]
txdatak0
txdeemph0
txdetectrx0
txelecidle0
txmargin0
txswing
WrDCMAddress_0[63:0]
WrDCMByteEnable_o[3:0]
WrDCMReadDataValid_i
WrDCMRead Data_i[31:0]
WrDCMRead_o
WrDCMWaitRequest_i
WrDCMWriteData_o[31:0]
WrDCMWrite_o
WrDTSAddress_i[7:0]
WrDTSBurstCount_i[4:0]
WrDTSChipSelect_i
WrDTXWaitRequest_o
WrDTSWriteData_i[255:0]
WrDTSWrite_i
Wr Descriptor Controller
Avalon-MM Master
Drives TX Slave to
Perform Single DWord
Transactions
to the Hard IP for PCIe
Descriptor Controller
Avalon-MM Slave
Receives Requested
Write Descriptors from the
DMA Read Master
Descriptor Controller
Avalon-MM Slave
Receives Requested
Read Descriptors from the
DMA Read Master
RdDTSAddress_i[7:0]
RdDTSBurstCount_i[4:0]
RdDTSChipSelect_i
RdDTXWaitRequest_o
RdDTSWriteData_o[255:0]
RdDTSWrite_i
4-2 V-Series DMA Avalon-MM DMA Interface to the Application Layer
UG-01154
2014.12.18
Altera Corporation Interfaces and Signal Descriptions
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