Altera V-Series Avalon-MM DMA - Manual (Page 76)

Figure 5-5: PCI Express AER Extended Capability Structure
Byte Offset 31:24 23:16 15:8 7:0
0x800
0x804
Uncorrectable Error Status Register
PCI Express Enhanced Capability Register
Uncorrectable Error Severity Register
Uncorrectable Error Mask Register 0x808
0x80C
0x810
0x814
0x818
0x81C
0x82C
0x830
0x834
Correctable Error Status Register
Correctable Error Mask Register
Advanced Error Capabilities and Control Register
Header Log Register
Root Error Command Register
Root Error Status Register
Error Source Identification Register
Correctable Error Source Identification Register
Figure 5-6: PCI Express Capability Structure - Byte Address Offsets and Layout
In the following table showing the PCI Express Capability Structure, registers that are not applicable to a
device are reserved.
Note: The Avalon-MM with DMA interface does not support Root Ports.
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
0x0AC
0x0B0
0x0B4
0x0B8
PCI Express Capabilities Register Next Cap Pointer
Device Capabilities
Device Status Device Control
Slot Capabilities
Root Status
Device Compatibilities 2
Link Capabilities 2
Link Status 2 Link Control 2
Slot Capabilities 2
Slot Status 2 Slot Control 2
31 24 23 16 15 8 7 0
PCI Express
Capabilities ID
Link Capabilities
Link Status Link Control
Slot Status Slot Control
Device Status 2 Device Control 2
Root Capabilities Root Control
UG-01154
2014.12.18
PCI Express Capability Structures 5-7
Registers Altera Corporation
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