Interfaces and signal descriptions – Altera V-Series Avalon-MM DMA User Manual
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Interfaces and Signal Descriptions
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2014.12.18
UG-01154
This chapter describes the top-level signals of V-Series the Avalon-MM DMA for PCI Express IP Core.
The Avalon-MM bridge includes high-performance, burst-capable Read DMA and Write DMA modules.
You can include the DMA Descriptor Controller that controls the Read DMA and Write DMA modules
in the Avalon-MM bridge or instantiate it separately. This variant is available for the following configura‐
tions:
• Gen1 x8
• Gen2 x4
• Gen2 x8
• Gen3 x4
• Gen3 x8
V-Series DMA Avalon-MM DMA Interface to the Application Layer
The following figures illustrate the signals in the variant that includes the high-performance, burst capable
Read DMA and Write DMA modules. The first figure illustrates this variant when the DMA Descriptor
Controller is embedded in the Avalon-MM bridge. The second figure illustrates this variant when the
DMA Descriptor Controller is instantiated separately. Depending on the device, the interface to the
Application Layer can be 128 or 256 bits.
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