Altera V-Series Avalon-MM DMA - Manual (Page 126)

Figure 9-1: Altera Transceiver Reconfiguration Controller Connectivity
The following figure shows the connections between the Transceiver Reconfiguration Controller instance
and the PHY IP Core for PCI Express instance for a ×4 variant.
Avalon-MM
Slave Interface
PHY IP Core for PCI Express
Lane 2
Lane 3
Lane 1
Lane 0
TX PLL
Transceiver Bank
to and from
Embedded
Controller
100-125 MHz
Transceiver Reconfiguration Controller
(Unused)
mgmt_clk_clk
mgmt_rst_reset
reconfig_mgmt_address[6:0]
reconfig_mgmt_writedata[31:0]
reconfig_mgmt_readdata[31:0]
reconfig_mgmt_write
reconfig_mgmt_read
reconfig_mgmt_waitrequest
reconfig_to_xcvr
reconfig_from_xcvr
Hard IP for PCI Express Variant
Hard IP for PCI Express
Trans-
action
Data
Link
PHY
As this figure illustrates, the
reconfig_to_xcvr[ 70-1:0]
and
reconfig_from_xcvr[ 46-1:0]
buses connect the two components. You must provide a 100–125 MHz free-running clock to the
mgmt_clk_clk
clock input of the Transceiver Reconfiguration Controller IP Core.
Initially, each lane and TX PLL require a separate reconfiguration interface. The parameter editor reports
this number in the message pane. You must take note of this number so that you can enter it as a
parameter value in the Transceiver Reconfiguration Controller parameter editor. The following figure
illustrates the messages reported for a Gen2 ×4 variant. The variant requires five interfaces: one for each
lane and one for the TX PLL.
Figure 9-2: Number of External Reconfiguration Controller Interfaces
When you instantiate the Transceiver Reconfiguration Controller, you must specify the required Number
of reconfiguration interfaces as the following figure illustrates.
9-2 Connecting the Transceiver Reconfiguration Controller IP Core
UG-01154
2014.12.18
Altera Corporation Transceiver PHY IP Reconfiguration
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