Altera V-Series Avalon-MM DMA User Manual
Page 47
Signal
Direction
Description
even if the V
VCCPGM
of the bank is not 3.3V if the following 2
conditions are met:
• The input signal meets the V
IH
and V
IL
specification for
LVTTL.
• The input signal meets the overshoot specification for 100°C
operation as specified by the “Maximum Allowed Overshoot
and Undershoot Voltage” section in volume 3 of the Stratix V
Device Handbook.
• The input signal meets the overshoot specification for 100°C
operation as defined in the device handbook.
Figure 4-7: Reset and Link Training Timing Relationships
The following figure illustrates the timing relationship between
npor
and the LTSSM L0 state.
npor
IO_POF_Load
PCIe_LinkTraining_Enumeration
dl_ltssm[4:0]
detect detect.active polling.active
L0
Note: To meet the 100 ms system configuration time, you must use the fast passive parallel configuration
scheme with CvP and a 32-bit data width (FPP x32) or use the CvP in autonomous mode.
Table 4-18: Status and Link Training Signals
Signal
Direction
Description
cfg_par_err
Output
Indicates that a parity error in a TLP routed to the internal
Configuration Space. This error is also logged in the Vendor
Specific Extended Capability internal error register. You must
reset the Hard IP if this error occurs.
The signal is not available for Arria V and Cyclone V devices.
4-16
Reset, Status, and Link Training Signals
UG-01154
2014.12.18
Altera Corporation
Interfaces and Signal Descriptions