Datasheet – Altera V-Series Avalon-MM DMA User Manual
Page 2
Datasheet
1
2014.12.18
UG-01154
V-Series Avalon-MM DMA Interface for PCIe Datasheet
Altera
®
V-Series FPGAs include a configurable, hardened protocol stack for PCI Express
®
that is
compliant with PCI Express Base Specification 2.1 or 3.0.
The V-Series Avalon
®
Memory-Mapped (Avalon-MM) DMA for PCI Express removes some of the
complexities associated with the PCIe protocol. For example, the IP core handles TLP encoding and
decoding. In addition, it includes Read DMA and Write DMA engines. If you have already architected
your own DMA system with the Avalon-MM interface, you may want to continue to use it. However, you
will probably benefit from the simplicity of having the DMA engines already implemented. Altera
recommends this variant for new users. Depending of the device you select, this variant is available in
Qsys for 128- and 256-bit interfaces to the Application Layer. The Avalon-MM interface and DMA
engines are implemented in FPGA soft logic.
Figure 1-1: V-Series PCIe Variant with Avalon-MM DMA Interface
The following figure shows the high-level modules and connecting interfaces for this variant.
Bridge
and DMA
Engine
PCIe Hard IP
Block
PIPE
Interface
PHY IP Core
for PCIe
(PCS/PMA)
Serial Data
Transmission
Application
Layer
(User Logic)
Avalon-MM with
DMA Interface
Note: This variant was renamed in the Quartus
®
II 14.0 release. The name in the Quartus II 13.1 release
was Avalon-MM 256-bit Hard IP for PCI Express IP Core.
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