Altera V-Series Avalon-MM DMA - Manual (Page 39)

Signal Name Direction Description
TxsWaitRequest_o Output When asserted, indicates that the Avalon-MM slave port is not
ready to respond to a read or write request.
Figure 4-6: TX Slave Interface Sends Status to Host
AvTxsChipSelect_i
AvTxsWrite_i
AvTxsAddress_i[27:0]
AvTxsByteEnable_i[3:0]
AvTxsWriteData_i[31:0]
AvTxsWaitRequest_o
AvTxsRead_i
AvTxsReadData_o[31:0]
AvTxsReadDataValid_o
1
32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals
The CRA port provides host access to the status registers of the Avalon-MM Bridge.
Table 4-5: Avalon-MM CRA Slave Interface Signals
Signal Name Directio
n
Description
CraRead_i Input Read enable
CraWrite_i Input Write request
CraAddress_i[13:0] Input An address space of 16 KBytes is allocated for the control
registers. Avalon-MM slave addresses provide address
resolution down to the width of the slave data bus.
CraWriteData_i[31:0] Input Write data
CraReadData_o[31:0] Output Read data lines
4-8 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals
UG-01154
2014.12.18
Altera Corporation Interfaces and Signal Descriptions
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