Altera V-Series Avalon-MM DMA User Manual
Page 40
Signal Name
Directio
n
Description
CraByteEnable_i[3:0]
Input Byte enable
CraWaitRequest_o
Output Wait request to hold off additional requests
CraChipSelect_i
Input Chip select signal to this slave
CraIrq_o
Output Interrupt request. A port request for an Avalon-MM interrupt.
Related Information
DMA Descriptor Controller Registers
Avalon-ST Descriptor Control Interface when Instantiated Separately
After fetching multiple descriptor entries from the Descriptor Table in the host memory, the Descriptor
Controller forms a single, 160-bit Descriptor Instruction and sends it to the Read DMA or Write DMA
engine.
Table 4-6: Descriptor Instruction Interface from Descriptor Controller to Read DMA Engine
Signal Name
Direction
Description
RdAstRxData_i[159:0]
Input
Specifies the descriptors for the Read DMA module. Refer to
DMA Descriptor Format table below for bit definitions.
RdAstRxValid_i
Input
When asserted, indicates that
RdAstRxData_i[159:0]
is valid.
RdAstRxReady_o
Output
When asserted, indicates that the Read DMA read module is
ready to receive a new descriptor.
Table 4-7: Descriptor Instruction Interface from Descriptor Controller to Write DMA Engine
Signal Name
Direction
Description
WrAstRxData_i[159:0]
Input
Specifies the descriptors for the Write DMA module. Refer to
DMA Descriptor Format table below for bit definitions.
WrAstRxValid_i
Input
When asserted, indicates that
WrAstRxData_i[159:0]
is valid.
WrAstRxReady_o
Output
When asserted, indicates that the Write DMA module engine is
ready to receive a new descriptor.
UG-01154
2014.12.18
Avalon-ST Descriptor Control Interface when Instantiated Separately
4-9
Interfaces and Signal Descriptions
Altera Corporation