Transceiver phy ip reconfiguration – Altera V-Series Avalon-MM DMA User Manual
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Transceiver PHY IP Reconfiguration
9
2014.12.18
UG-01154
As silicon progresses towards smaller process nodes, circuit performance is affected by variations due to
process, voltage, and temperature (PVT). Consequently, Gen3 designs require offset cancellation and
adaptive equalization (AEQ) to ensure correct operation. Altera’s Qsys example designs all include
Transceiver Reconfiguration Controller and Altera PCIe Reconfig Driver IP cores that automatically
perform these functions during the LTSSM equalization states.
As silicon progresses towards smaller process nodes, circuit performance is affected by variations due to
process, voltage, and temperature (PVT). Designs typically require offset cancellation to ensure correct
operation. At Gen2 data rates, designs also require DCD calibration. Altera’s Qsys example designs all
include Transceiver Reconfiguration Controller and Altera PCIe Reconfig Driver IP cores to perform
these functions.
Connecting the Transceiver Reconfiguration Controller IP Core
The Transceiver Reconfiguration Controller IP Core is available for V-series devices and can be found in
the Interface Protocols/Transceiver PHY category in the IP Catalog. When you instantiate the
Transceiver Reconfiguration Controller the Enable offset cancellation block and Enable PLL calibration
options are enabled by default. For Gen3 variants, you should also turn on Enable adaptive equalization
(AEQ) block.
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