Altera V-Series Avalon-MM DMA - Manual (Page 59)

Channel Placement in Cyclone V Devices
Figure 4-14: Cyclone V Gen1 and Gen2 Channel Placement Using the CMU PLL
In the following figures the channels shaded in blue provide the transmit CMU PLL generating the high-
speed serial clock.
Ch5
Ch3
Ch2
Ch1
Ch0
CMU PLL
PCIe Hard IP
Ch0
Ch1
Ch5
Ch3
Ch2
Ch1
Ch0
CMU PLL
PCIe Hard IP
Ch0
Ch1
Ch2
Ch3
Ch5
Ch3
Ch2
CMU PLL
Ch0
Ch4
PCIe Hard IP
x1
x2
x4
Ch0
You can assign other protocols to unused channels the if data rate and clock specification exactly match
the PCIe configuration.
Physical Layout of Hard IP in Arria V GZ Devices
Arria V GZ devices include one Hard IP for PCI Express IP core. The following figures illustrate the
placement of the PCIe IP core, transceiver banks, and channels.
4-28 Channel Placement in Cyclone V Devices
UG-01154
2014.12.18
Altera Corporation Interfaces and Signal Descriptions
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