Altera V-Series Avalon-MM DMA - Manual (Page 86)

1. Program the
RD_DMA_LAST_PTR
= 63.
2. Program the
RD_DMA_LAST_PTR
= 127.
3. Poll the status dword for read descriptor 63.
4. Poll the status dword for read descriptor 127.
In systems that support out-of-order Read Completions the Descriptor Controller may complete
descriptors out of order. Consequently, the
done
status stored for descriptor does not necessarily
mean that descriptors and have also completed. You must request the completion status for
every descriptor by writing the descriptor ID for every descriptor to
RD_DMA_LAST_PTR
or
WR_DMA_LAST_PTR
. Many commercial system Root Ports do return out-of-order Read Completions based
on optimized accesses to host memory channels.
Table 5-15: DMA Descriptor Controller Registers for Read DMAs
The following tables describes the registers in the internal DMA Descriptor Controller. When the DMA
Descriptor Controller is externally instantiated, these registers are accessed through a BAR. The offsets must be
added to the base address for the read and write controllers. When the Descriptor Controller is internally
instantiated these registers are accessed through BAR0. The read controller is at offset 0x0000. The write
controller is at offset 0x0100 when instantiated internally.
Address
Offset
Register Access Description
0x000
0
RC Read Status and Descriptor Base
(Low)
R/W Specifies the lower 32-bits of the base
address of the read status and descriptor
table in the Root Complex memory. This
address must be on a 32-byte boundary.
Internal software must program this
register after programming the upper 32
bits at offset 0x4.
0x000
4
RC Read Status and Descriptor Base
(High)
R/W Specifies the upper 32-bits of the base
address of the read status and descriptor
table in the Root Complex memory.
Software must program this register
before programming the lower 32 bits of
this register.
0x000
8
EP Read Descriptor FIFO Base (Low) RW Specifies the lower 32 bits of the base
address of the read descriptor FIFO in
Endpoint memory. The Read DMA
fetches the descriptors from Root
Complex memory. The address must be
the Avalon-MM address of the Descriptor
Controller's Read Descriptor Table
Avalon-MM Slave Port as seen by the
Read DMA Avalon-MM Master Port. You
must program this register after program‐
ming the upper 32 bits at offset 0x8.
UG-01154
2014.12.18
DMA Descriptor Controller Registers 5-17
Registers Altera Corporation
Send Feedback