Physical layer interface signals, Transceiver reconfiguration – Altera V-Series Avalon-MM DMA User Manual
Page 52
Signal
Direction
Description
MSIControl_o[15:0]
Output
Provides system software control of the MSI messages as defined
in Section 6.8.1.3 Message Control for MSI in the PCI Local Bus
Specification, Rev. 3.0. The following fields are defined:
•
MSIControl_o[15:9]
: Reserved
•
MSIControl_o[8]
: Per-Vector Masking Capable
•
MSIControl_o[7]
: 64-Bit Address Capable
•
MSIControl_o[6:4]
: Multiple Message Enable
•
MSIControl_o[3:1]
: MSI Message Capable
•
MSIControl_o[0]
: MSI Enable
Physical Layer Interface Signals
Altera provides an integrated solution with the Transaction, Data Link and Physical Layers. The IP
Parameter Editor generates a SERDES variation file,
or .vhd , in addition to the Hard
IP variation file,
or
.vhd
. The SERDES entity is included in the library files for PCI Express.
Transceiver Reconfiguration
Dynamic reconfiguration compensates for variations due to process, voltage and temperature (PVT).
Among the analog settings that you can reconfigure are V
OD
, pre-emphasis, and equalization.
You can use the Altera Transceiver Reconfiguration Controller to dynamically reconfigure analog
settings. For more information about instantiating the Altera Transceiver Reconfiguration Controller IP
core refer to Hard IP Reconfiguration .
Table 4-20: Transceiver Control Signals
In this table,
Signal Name
Direction
Description
reconfig_from_
xcvr[(
Output
Reconfiguration signals to the Transceiver Reconfiguration
Controller.
reconfig_to_xcvr[(
70)-1:0]
Input
Reconfiguration signals from the Transceiver Reconfiguration
Controller.
reconfig_clk_locked
Output
When asserted, indicates that the PLL that provides the fixed
clock required for transceiver initialization is locked. The
Application Layer should be held in reset until
reconfig_clk_
locked
is asserted.
The following table shows the number of logical reconfiguration and physical interfaces required for
various configurations. The Quartus II Fitter merges logical interfaces to minimize the number of physical
interfaces configured in the hardware. Typically, one logical interface is required for each channel and one
UG-01154
2014.12.18
Physical Layer Interface Signals
4-21
Interfaces and Signal Descriptions
Altera Corporation