Altera V-Series Avalon-MM DMA User Manual
Page 60
Figure 4-15: Physical Layout of Hard IP in Arria V GZ Devices
6 Ch
6 Ch
PCIe
Hard
IP
GXB_R2
GXB_L2
GXB_L1
GXB_L0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
6 Ch
6 Ch
GXB_R1
GXB_R0
24
Channels
6 Ch
6 Ch
36 Channels
Notes:
1. 12-channel devices use banks L0 and L1.
2. All channels capable of backplane support up to 12.5 Gbps.
Refer to Transceiver Architecture in Arria V Devices for comprehensive information on the number of
Hard IP for PCIe IP cores available in various Arria V GZ packages.
Refer to Channel Utilization for Data and Clock Routing in Arria V GZ and Stratix V Devices for
additional information about channel and PLL utilization.
Related Information
•
Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
on page 4-31
•
•
Physical Layout of Hard IP in Stratix V GX/GT/GS Devices
Stratix V devices include one, two, or four Hard IP for PCI Express IP cores. The following figures
illustrate the placement of the PCIe IP cores, transceiver banks, and channels for the largest Stratix V
devices. Note that the bottom left hard IP block includes the CvP functionality for flip chip packages. For
other package types, the CvP functionality is in the bottom right block. All other Hard IP blocks do not
include the CvP functionality.
UG-01154
2014.12.18
Physical Layout of Hard IP in Stratix V GX/GT/GS Devices
4-29
Interfaces and Signal Descriptions
Altera Corporation