Altera V-Series Avalon-MM DMA User Manual
Page 138
Date
Version
Changes Made
Made the following changes to the user guide:
• Removed 125 MHz clock as optional
refclk
frequency in V-
Series devices. V-Series devices support an 100 MHz reference
clock as specified by the PCI Express Base Specification, Rev 3.0
• Corrected values for Maximum payload size parameter. The sizes
available are 128 or 256 bytes.
• Enhanced definition of Device ID and Sub-system Vendor ID to
say that these registers are only valid in the Type 0 (Endpoint)
Configuration Space.
• Removed 125 MHz clock as optional
refclk
frequency in V-
Series devices. V-Series devices support an 100 MHz reference
clock as specified by the PCI Express Base Specification, Rev 3.0.
• Added Next Steps in Creating a Design for PCI Express to
Datasheet chapter.
• Removed the Transaction Layer Protocol Details chapter. This
information only applies to the Avalon-ST interface.
• Removed
txdatavalid0
signal from the PIPE interface. This
signal is not available.
• Removed references to the MegaWizard
®
Plug-In Manager. In
14.0 the IP Parameter Editor Powered by Qsys has replaced the
MegaWizard Plug-In Manager.
• Added definitions for
test_in[2]
,
test_in[6]
and
test_in[7]
.
• Corrected interface widths in the Performance and Resource
Utilization V-Series Avalon-MM DMA for PCI Express table in the
Datasheet: V-Series Avalon-MM DMA for PCIe chapter.
• Removed discussion of
pclk
. This clock is not customer accessible
in Arria 10 devices.
• Corrected Reset Controller in V-Series Devices figure in Reset and
Clocks chapter.
• Corrected bit definitions for
CvP Status
register.
• Removed PLL from channel placement figures.
• Added fast passive parallel (FPP) to supported configuration
schemes in CvP in Arria 10 Devices figure.
• Updated Power Supply Voltage Requirements table.
UG-01154
2014.12.18
Revision History for the Avalon-MM Interface with DMA
B-3
Additional Information
Altera Corporation