Altera V-Series Avalon-MM DMA - Manual (Page 57)

Channel Placement in Arria V Devices
Figure 4-11: Arria V Gen1 and Gen2 Channel Placement Using the CMU PLL
In the following figures the channels shaded in blue provide the transmit CMU PLL generating the high-
speed serial clock.
Ch5
Ch3
Ch2
Ch1
Ch0
CMU PLL
PCIe Hard IP
Ch0
Ch1
Ch5
Ch3
Ch2
Ch1
Ch0
CMU PLL
PCIe Hard IP
Ch0
Ch1
Ch2
Ch3
Ch5
Ch3
Ch2
Ch1
Ch0
CMU PLL
Ch0
Ch1
Ch2
Ch3
Ch11
Ch9
Ch8
Ch7
Ch6
Ch10
PCIe Hard IP
Ch5
Ch6
Ch7
Ch4
Ch5
Ch3
Ch2
CMU PLL
Ch0
Ch4
PCIe Hard IP
x1
x8
x2
x4
Ch0
You can assign other protocols to unused channels the if data rate and clock specification exactly match
the PCIe configuration.
Physical Layout of Hard IP in Cyclone V Devices
Cyclone V devices include one or two Hard IP for PCI Express IP cores. The following figures illustrate
the placement of the PCIe IP cores, transceiver banks, and channels. Note that the bottom left IP core
includes the CvP functionality. The other Hard IP blocks do not include the CvP functionality.
Transceiver banks include six channels. Within a bank, channels are arranged in 3-packs. GXB_L0
contains channels 0–2, GXB_L1 includes channels 3–5, and so on.
4-26 Channel Placement in Arria V Devices
UG-01154
2014.12.18
Altera Corporation Interfaces and Signal Descriptions
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