Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 71)

7–4 Chapter 7: Functional Description
Interfaces
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
In the MAC, the Avalon-ST interface acts as a sink in the transmit datapath and source
in the receive datapath. These interfaces are 64 bits wide and support packets,
backpressure, and error. The ready latency on these interfaces is 0 and the MAC
expects the empty signal to contain a valid value.
f For more information about the Avalon-ST interface, refer to the Avalon Interface
Specifications .
7.2.2. SDR XGMII
The network-side interface of the 10GbE MAC implements the SDR version of the
XGMII protocol. The SDR XGMII consists of 64-bit data bus and 8-bit control bus
operating at 156.25 MHz. The data bus carries the MAC frame; the most significant
byte occupies the least significant lane.
7.2.3. GMII
The network-side interface of the 1GbE MAC implements the GMII protocol for the
1Gpbs mode. The GMII defines speeds up to 1000 Mbit/s, implemented using an
eight-bit data interface operating at 125 MHz.
7.2.4. MII
The network-side interface of the 10M/100MbE MAC implements the MII protocol
for the 10 Mbps and 100 Mbps mode. The MII defines speeds up to 10Mbit/s and
100Mbit/s. The speed is implemented using a four-bit data interface operating at
125 MHz, with the clock enable signal to divide the clock to 25 MHz for 100 Mbps and
2.5 MHz for 10 Mbps.
7.2.5. Avalon-MM Control and Status Register Interface
The Avalon-MM control and status register interface is an Avalon-MM slave port. This
interface uses word addressing which provides host access to 32-bit configuration and
status registers, and statistics counters.