Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 172)

Info–2 Additional Information
Document Revision History
10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation
May 2013 3.2
■ Added device support for Arria V SoC and Cyclone V SoC devices.
■ Added Stratix V performance and resource utilization data for 10GbE MAC and
10M-10GbE MAC in
Table 1–7 and Table 1–8 on page 1–6 .
■ Added information for the Enable Multi-Speed 10M-10Gb MAC parameter in Table 2–1
on page 2–6 .
■ Added information about minimum IPG for receive path in Table 7–1 on page 7–11 .
■ Added information about 10 Mbps and 100 Mbps in “IEEE 1588v2” on page 7–21 .
■ Renamed rx_framedecoder_control register to rx_frame_control register.
■ Added information about 10 Mbps and 100 Mbps in Table 8–5 on page 8–18 , Table 9–13
on page 9–25 , and Table 9–14 on page 9–25 .
■ Added information about PMA analog and digital delay in Table 8–6 and Table 8–7 on
page 8–19 .
■ Updated Figure 9–1 to include MII signals and the speed_sel signal.
■ Added description about MII signals for 10 Mbps and 100 Mbps modes in Table 9–6 .
■ Added description about the speed_sel signal in “10M-10GbE MAC Speed Control
Signal” on page 9–20 .
■ Added timing diagrams for the IEEE 1588v2 timestamp of frames observed on the TX
path in
Figure 9–9 through Figure 9–12 on page 9–30 .
■ Added 10M-10GbE MAC with IEEE 1588v2 Design Example .
■ Added the following sections: “Sharing TX and RX Clocks for Multi-Port System Design”
on page 10–2 and “Sharing Reference Clocks for Multi-Port System Design” on
page 10–3 .
■ Updated ToD information in Table B–5 on page B–3 .
■ Added information for the following registers: DriftAdjust and DriftAdjustRate, in
Table B–6 on page B–4 .
■ Added Appendix D, ToD Synchronizer .
November 2012 3.1.1 Edited the description for the tx_transfer_status signal.
November 2012 3.1
■ Added support for Arria V and Stratix V devices.
■ Added information for the following GUI parameters: 1G/10G MAC, Enable Time
Stamping, Enable PTP 1-Step Clock Support, and Timestamp Fingerprint Width, in
Table 2-1.
■ Updated the following design examples:10GbE MAC Design Examples and 1G/10GbE
MAC Design Example.
■ Added the following chapters: 10GbE MAC with IEEE 1588v2 Design Example and
1G/10GbE MAC with IEEE 1588v2 Design Example.
■ Added description about GMII signals for 1 Gbps mode in Table 9-5.
■ Added MAC registers with IEEE 1588v2 feature for 1 Gbps mode in Table 8-5.
■ Updated RX ingress timestamp and TX egress timestamp interface signals for IEEE
1588v2 in Table 9-9 and Table 9-10.
■ Added TX instant control timestamp interface signals for IEEE 1588v2 in Table 9-11.
■ Updated Figure 9-1 to include GMII and IEEE 1588v2 signals.
■ Added Appendix C, Packet Classifier.
July 2012 3.0.1 Added the Early Access 1GbE MAC feature.
Date Version Changes